Complex industrial processes, such as those used for the manufacture of semiconductor integrated circuit chips, typically employ several tens to hundreds of individual steps, process parameters for many, if not most, of which must be tightly controlled. Because the testing of a semiconductor wafer is not conducted until after the wafer has undergone a large number of critical processing steps, then, when a defective wafer is detected during testing, it is ordinarily not possible to immediately determine at what point in the process the defect was introduced, or what caused the defect. Moreover, the cause of the defect may not necessarily be related to a problem with a particular piece of manufacturing equipment. The problem could be the result of operator error. Whatever the cause, a failed device means a reduction in process yield.
Because the number of variables that could cause a chip to be declared as `failed` is so large, attempting to track processed wafers through their respective processing flow paths by means of a conventional numerical analysis of parameter data for each node in the process is an extremely cumbersome, if not impossible, task.